This document describes the features, architecture, and programming model of the Freescale Vybrid microprocessor (MPU).

This document is primarily for system architects and software application developers who are using or considering using this device in a system.

Main features include

• Cortex-A5 @500MHz (1.57 DMIPS/MHz) with TrustZone with 32 KB I-Cache/32 KB D-Cache

• Neon Media Processing Engine (MPE) co-processor and double precision Floating Point Unit (FPU)

• Cortex-M4 @ 167 MHz with 16 KB I-Cache/16 KB D-Cache

• 1.5 MB on-chip SRAM of which 512 KB optionally supports ECC

• Support for LPDDR2/DDR3

• Dual TFT display up to SVGA and optional 40×4 and 38×6 Segmented LCD

• Dual 10/100 Ethernet with on-chip L2 Switch

• Dual USB OTG with on-chip HS PHY and on-chip HS/FS/LS PHY

• Advanced Security supporting Symmetric with on-chip Tamper detection

• Rich set of communication peripherals and general purpose features

• Advanced digital audio support with multiple audio interfaces and hardware asynchronous sample-rate converter co-processor.

• Multiple package options that include 176 LQFP, and 364 BGA